? semiconductor components industries, llc, 2015 november, 2015 ? rev. 2 1 publication order number: LM321/d LM321 single channel operational amplifier LM321 is a general purpose, single channel op amp with internal compensation and a true differential input stage. this op amp features a wide supply voltage ranging from 3 v to 32 v for single supplies and 1.5 to 16 v for split supplies, suiting a variety of applications. LM321 is unity gain stable even with large capacitive loads up to 1.5 nf. LM321 is available in a space-saving tsop?5/sot23?5 package. features ? wide supply voltage range: 3 v to 32 v ? short circuit protected outputs ? true differential input stage ? low input bias currents ? internally compensated ? single and split supply operation ? unity gain stable with 1.5 nf capacitive load ? this device is pb-free, halogen free/bfr free and is rohs compliant typical applications ? gain stage ? active filter ? signal processing marking diagram www. onsemi.com tsop?5 case 483 pin connection ady = specific device code a = assembly location y = year w = work week = pb-free package 1 5 adyayw (note: microdot may be in either location) 1 5 vcc in+ vee out in? 1 2 3 5 4 device package shipping ? ordering information LM321sn3t1g tsop?5 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
LM321 www. onsemi.com 2 table 1. absolute maximum ratings (over operating free-air temperature, unless otherwise stated) parameter rating unit supply voltage 36 v input and output pins input voltage v ee ? 0.3 to 32 v input current 10 ma output short circuit duration (note 1) continuous temperature operating temperature ?40 to +125 c storage temperature ?65 to +150 c junction temperature ?65 to +150 c esd ratings (note 2) human body model (hbm) 200 v charged device model (cdm) 800 v machine model (mm) 100 v other ratings latch-up current (note 3) 100 ma msl level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. short circuits can cause excessive heating and eventual destruction. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per jedec standard: jesd22?a114 esd machine model tested per jedec standard: jesd22?a115 3. latch-up current tested per jedec standard: jesd78 table 2. thermal information (note 4) parameter symbol package value unit junction to ambient ja tsop?5/sot23?5 235 c/w 4. as mounted on an 80 80 1.5 mm fr4 pcb with 650 mm 2 and 2 oz (0.034 mm) thick copper heat spreader. following jedec jesd/eia 51.1, 51.2, 51.3 test guidelines. table 3. recommended operating conditions parameter symbol range unit supply voltage (v cc ? v ee ) v s 3 to 32 v specified operating range t a ?40 to 85 c common mode input voltage range v cm v ee to v cc ?1.7 v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability.
LM321 www. onsemi.com 3 table 4. electrical characteristics ? v s = 5 v (at t a = +25 c, r l = 10 k connected to mid-supply, v cm = v out = mid-supply, unless otherwise noted. boldface limits apply over the specified temperature range, t a = ?40 c to 85 c, guaranteed by characterization and/or design.) parameter symbol conditions min typ max unit input characteristics offset voltage v os v s = 5 v, v cm =v ee to v cc ? 1.7 v t a = 25 c t a = ?40 c to 85 c ? ? 0.3 ? 7 9 mv offset voltage drift vs temp v os / t t a = ?40 c to 85 c ? 7 ? v/ c input bias current i ib t a = 25 c t a = ?40 c to 85 c ? ? ?10 ? ? ?500 na input offset current i os t a = 25 c t a = ?40 c to 85 c ? ? 1 ? ? 150 na common mode rejection ratio cmrr v cm = v ee to v cc ? 1.7 v 65 85 ? db input resistance r in differential common mode ? ? 85 300 ? ? g input capacitance c in differential common mode ? ? 0.6 1.6 ? ? pf output characteristics open loop voltage gain a vol ? 100 ? db open loop output impedance z out_ol f = ugbw, i o = 0 ma ? 1,200 ? output voltage high v oh r l = 2 k to v ee r l = 10 k to v ee v cc ?1.8 v cc ?1.8 v cc ?1.4 v cc ?1.4 ? ? v output voltage low v ol r l = 10 k to v cc ? v ee +0.8 v ee +1.0 v output current capability i o sinking current v s = 5 v v s = 15 v 10 10 20 20 ? ? ma output current capability i o sourcing current v s = 5 v v s = 15 v 20 20 40 40 ? ? ma capacitive load drive c l phase margin = 15 ? 1,500 ? pf noise performance voltage noise density e n f in = 1 khz ? 40 ? nv/ hz dynamic performance gain bandwidth product gbwp c l = 25 pf, r l to v cc ? 750 ? khz gain margin a m c l = 25 pf, r l to v cc ? 14 ? db phase margin m c l = 25 pf, r l to v cc ? 60 ? slew rate sr c l = 25 pf, r l = ? 0.3 ? v/ s power supply power supply rejection ratio psrr v s = 5 v to 32 v 62 100 ? db quiescent current i q no load ? 0.25 0.5 ma product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
LM321 www. onsemi.com 4 table 5. electrical characteristics ? v s = 32 v (at t a = +25 c, r l = 10 k connected to mid-supply, v cm = v out = mid-supply, unless otherwise noted. boldface limits apply over the specified temperature range, t a = ?40 c to 85 c, guaranteed by characterization and/or design.) parameter symbol conditions min typ max unit input characteristics offset voltage v os v s =32v, v cm =v ee to v cc ? 1.7 v t a = 25 c t a = ?40 c to 85 c ? ? 0.3 ? 7 9 mv offset voltage drift vs temp v os / t t a = ?40 c to 85 c ? 7 ? v/ c common mode rejection ratio cmrr v cm = v ee to v cc ? 1.7 v ? 100 ? db output characteristics open loop voltage gain a vol t a = 25 c t a = ?40 c to 85 c ? 84 100 ? ? ? db open loop output impedance z out_ol f = ugbw, i o = 0 ma ? 2,000 ? output voltage high v oh r l = 2 k to v ee r l = 10 k to v ee v cc ?2.5 v cc ?2.5 v cc ?2.0 v cc ?1.5 ? ? v output voltage low v ol r l = 10 k to v cc ? v ee +1.0 v ee +1.5 v capacitive load drive c l phase margin = 15 ? 1,500 ? pf noise performance voltage noise density e n f in = 1 khz ? 40 ? nv/ hz total harmonic distortion + noise thd+n v s =30v, f in = 1 khz, r l to v cc ? 0.02 ? % dynamic performance gain bandwidth product gbwp c l = 25 pf, r l to v cc ? 900 ? khz gain margin a m c l = 25 pf, r l to v cc ? 18 ? db phase margin m c l = 25 pf, r l to v cc ? 66 ? slew rate sr c l = 25 pf, r l = ? 0.4 ? v/ s power supply power supply rejection ratio psrr v s = 5 v to 32 v 62 100 ? db quiescent current i q no load, v s =32v ? 0.3 1.2 ma product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
LM321 www. onsemi.com 5 typical characteristics figure 1. open loop gain and phase margin vs. frequency figure 2. cmrr vs. frequency figure 3. inverting large signal step response figure 4. inverting small signal step response figure 5. phase margin vs. load capacitance figure 6. voltage noise density vs. frequency frequency (hz) phase margin ( ) a vol (db) 10 0 ?60 100 1k 10k 100k 1m 10m ?40 ?20 0 20 40 60 80 100 120 30 60 90 120 150 180 210 240 270 r l = 10 k c l = 25 pf v s = 3 v, gain v s = 5 v, gain v s = 32 v, gain v s = 3 v, phase v s = 5 v, phase v s = 32 v, phase phase margin frequency (hz) cmrr (db) 10 0 10 20 30 40 50 60 70 80 90 100 110 100 1k 10k 100k 1m v s = 3 v v s = 5 v v s = 32 v time ( s) voltage (v) ?10 ?4 0 102030405060708090100 ?3 ?2 ?1 0 1 2 3 4 v s = 10 v r l = 10 k c l = 15 pf input output time ( s) voltage (v) ?2 ?0.1 02468101214 input output v s = 5.0 v r l = 10 k c l = 15 pf ?0.08 ?0.06 ?0.04 ?0.02 0.0 0.02 0.04 0.06 0.08 0.1 load capacitance (pf) phase margin ( ) 100 0 200 300 500 1000 1500 10 20 30 40 50 60 v s = 3 v v s = 5 v v s = 32 v frequency (hz) voltage noise density (nv/ hz) 1 10 10 100 1k 10k 100k 100 1000 v s = 3 v v s = 5 v v s = 32 v a v = 11 v/v r l = 10 k
LM321 www. onsemi.com 6 typical characteristics figure 7. thd+n vs. frequency figure 8. quiescent current vs. temperature figure 9. input offset voltage vs. common mode voltage at 3 v supply figure 10. input offset voltage vs. common mode voltage at 5 v supply figure 11. input offset voltage vs. common mode voltage at 32 v supply figure 12. input bias and offset current vs. temperature frequency (hz) thd+n (%) 10 10 100 1k 10k 100k 100 1000 temperature ( c) quiescent current (ma) 0.00 ?40 ?20 0 20 40 60 80 100 0.05 0.10 0.15 0.20 0.25 0.30 0.35 v s = 3 v v s = 5 v v s = 32 v common mode voltage (v) input offset voltage (mv) ?0.6 0 0.1 0.2 0.25 0.5 0.7 1 1.25 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 t= ?40 c t= 25 c t= 85 c 1.3 1.4 1.5 v s = 3 v common mode voltage (v) input offset voltage (mv) ?0.6 0 0.5 1 1.5 2 2.5 3 3.5 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 t= ?40 c t= 25 c t= 85 c v s = 5 v common mode voltage (v) input offset voltage (mv) ?0.6 0 5 10 15 20 25 30 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 t= ?40 c t= 25 c t= 85 c v s = 32 v temperature ( c) current (na) ?10 ?40 ?20 0 20 40 60 80 ?8 ?6 ?4 ?2 0 2 4 i ib? i ib+ i os v cm = v s /2 6 8 10 100
LM321 www. onsemi.com 7 typical characteristics figure 13. high level output voltage swing vs. output current at 3 v supply figure 14. low level output voltage swing vs. output current at 3 v supply figure 15. high level output voltage swing vs. output current at 5 v supply figure 16. low level output voltage swing vs. output current at 5 v supply figure 17. high level output voltage swing vs. output current at 32 v supply figure 18. low level output voltage swing vs. output current at 5 v supply32 output source current (ma) v cc ? v oh (v) 0 0 5 10 15 20 25 30 0.5 1.0 1.5 2.0 2.5 3.0 t= ?40 c t= 25 c t= 85 c v s = 3 v output sink current (ma) v ol ? v ee (mv) 0 0 5 10 15 20 200 400 600 800 1000 1200 t= ?40 c t= 25 c t= 85 c v s = 3 v 1400 output source current (ma) v cc ? v oh (v) 0 0 5 10 30 15 25 20 0.5 1.0 1.5 2.0 2.5 3.0 t= ?40 c t= 25 c t= 85 c v s = 5 v 3.5 4.0 4.5 5.0 output sink current (ma) v ol ? v ee (mv) 0 0 5 10 15 20 200 400 600 800 1000 1200 t= ?40 c t= 25 c t= 85 c v s = 5 v 1400 1600 1800 output source current (ma) v cc ? v oh (v) 0 0 5 10 30 15 25 20 0.5 1.0 1.5 2.0 2.5 3.0 t= ?40 c t= 25 c t= 85 c v s = 32 v 3.5 4.0 4.5 5.0 output sink current (ma) v ol ? v ee (v) 0 03 9 30 15 21 18 1 2 3 4 5 6 t= ?40 c t= 25 c t= 85 c v s = 32 v 7 8 612 2427
LM321 www. onsemi.com 8 application information circuit description the LM321 is made using two internally compensated, two?stage operational amplifiers. the first stage of each consists of dif ferential input devices q20 and q18 with input buffer transistors q21 and q17 and the differential to single ended converter q3 and q4. the first stage performs not only the first stage gain function but also performs the level shifting and transconductance reduction functions. by reducing the transconductance, a smaller compensation capacitor (only 5.0 pf) can be employed, thus saving chip area. the transconductance reduction is accomplished by splitting the collectors of q20 and q18. another feature of this input stage is that the input common mode range can include the negative supply or ground, in single supply operation, without saturating either the input devices or the differential to single?ended converter. the second stage consists of a standard current source load amplifier stage. each amplifier is biased from an internal?voltage regulator which has a low temperature coefficient thus giving each amplifier good temperature characteristics as well as excellent power supply rejection. output bias circuitry v cc v ee /gnd inputs q2 q3 q4 q5 q26 q7 q8 q6 q9 q11 q10 q1 2.4 k q25 q22 40 k q13 q14 q15 q16 q19 5.0 pf q18 q17 q20 q21 2.0 k q24 q23 q12 25 figure 19. LM321 representative schematic diagram
LM321 www. onsemi.com 9 LM321 has a class b output stage, which is comprised of push?pull transistors. this type of output is inherently subject to crossover distortion near mid?rail where neither push or pull transistors are conducting. several techniques can be used to minimize crossover distortion. connecting the output load to either the positive or negative supply rail instead of mid?rail can reduce the crossover distortion. additionally, increasing the load resistance relatively decreases the amount of crossover distortion. vcc vee out figure 20. simplified class b output figure 21. sine wave with crossover distortion
LM321 www. onsemi.com 10 package dimensions tsop?5 case 483 issue l notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions a and b do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimension a. 5. optional construction: an additional trimmed lead is allowed in this location. trimmed lead not to extend more than 0.2 from body. dim min max millimeters a 3.00 bsc b 1.50 bsc c 0.90 1.10 d 0.25 0.50 g 0.95 bsc h 0.01 0.10 j 0.10 0.26 k 0.20 0.60 m 0 10 s 2.50 3.00 123 54 s a g b d h c j 0.7 0.028 1.0 0.039 mm inches scale 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.20 5x c ab t 0.10 2x 2x t 0.20 note 5 c seating plane 0.05 k m detail z detail z top view side view a b end view on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 LM321/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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